Apple Inc.

Qualcomm Incorporated

California Institute of Technology

Wilinx Corporation

Rambus Inc.

Lattice Semiconductor Corporation

Abbas Komijani

Hongrui Wang

Sohrab Emami-Neyestanak

Seyed Ali Hajimiri

Yashar Rajavi

Mohammad Bagher Vahid Far

Reetika Kumari Agarwal

Scott D Kee

Alireza Khalili

Amirpouya Kavousian

Saihua Lin

Rahim Bagheri

Masoud Djafari

Edris Rostami

Aliazam Abbasfar

Arun Sridhar Natarajan

Ichiro Aoki

Xinhua Chen

Ichiri Aoki

Cheng-Han Wang

Emmanouil Terrovitis

Behzad Biglarbegian

Ahmad Mirzaei

Jesse Aaron Richmond

Mazhareddin Taghivand

Thinh Cat Nguyen

Richard Chang

Lalitkumar Nathawad

Mohamed Abouzied

Hideya Oshima

Chan Hong Park

Justin A Hwang

Xiang Guan

Mohammad Mahdi Ghahramani

Junjun Li

Mahdi Bagheri

Aydin Babakhani

Chen Zhai

Seyed Hossein Miri Lavasani

Seyed-Ali Hajimiri

An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and/or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.

Eddy current mitigation for on-chip inductors

Wireless circuitry can include a radio-frequency amplifier and a power detection circuit coupled to an output of the radio-frequency amplifier. The power detection circuit can include an input transistor, a biasing circuit configured to output a bias voltage for the input transistor and configured to track temperature and voltage variations, and a non-linearity cancellation component configured to generate a current that at least partially cancels a non-linear current associated with the input transistor. The input transistor may be an n-type transistor, and the non-linearity cancellation component may be a p-type metal-oxide-semiconductor capacitor. The biasing circuit can include n-type and p-type diode-connected bias transistors.

Radio-frequency power detector with non-linearity cancellation

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

Partial-fractional phase-locked loop with sigma delta modulator and finite impulse response filter

Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

Split input amplifier for protection from DC offset

In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.

Systems and methods for improved charge pump phase-locked loop phase stability

An electronic device may include a transceiver with mixer circuitry that up-converts or down-converts signals based on a voltage-controlled oscillator (VCO) signal. The transceiver circuitry may include first, second, third, and fourth VCOs. Each VCO may include a VCO core that receives a control voltage and an inductor coupled to the VCO core. Fixed linear capacitors may be coupled between the VCO cores. A switching network may be coupled between the VCOs. Control circuitry may place the VCO circuitry in one of four different operating modes and may switch between the operating modes to selectively control current direction in each of the inductors. The VCO circuitry may generate the VCO signal within a respective frequency range in each of the operating modes. The VCO circuitry may exhibit a relatively wide frequency range across all of the operating modes while introducing minimal phase noise to the system.

Wideband voltage-controlled oscillator circuitry

Voltage-controlled oscillation circuitry includes multiple cores and multiple mode or gain boosters coupled between the multiple cores. To prevent an undesired operating mode of the voltage-controlled oscillation circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), the mode boosters may increase a desired gain of the desired operating mode and decrease an undesired gain of the undesired operating modes. In particular, mode boosters coupled to terminals of the cores that are associated with the desired operating mode may be enabled, while mode boosters coupled to terminals of the cores that are associated with the undesired operating mode may be disabled.

Multi-core oscillator with enhanced mode robustness

To increase the operating frequency range of the DLL while decreasing varactor sizes, coarse tuning circuitry may be implemented in a delay-locked loop (DLL). The DLL may include a voltage-controlled delay line (VCDL) including multiple switched capacitors coupled in parallel to each other. An electrical ground may be coupled to the parallel switched capacitors at a first node and a buffer and variable capacitor may be coupled to the parallel switched capacitors at a second node. The coarse tuning circuitry may be electrically coupled to a phase detector and to the multiple switched capacitors of the VCDL, such that the coarse tuning circuitry may receive a signal (e.g., an indication of a phase) from the phase detector and may adjust switched capacitor loading based on the signal received from the phase detector. Such a DLL implementation may increase DLL tuning range and decrease phase noise, among other advantages.

Systems and methods for providing a delay-locked loop with coarse tuning technique

Radio frequency filtering circuitry blocks certain frequencies in an outgoing signal so that the signal may be transmitted over a desired frequency. The radio frequency filtering circuitry includes a first inductor having a first coil and a second inductor coupled to and disposed within the first coil. The second inductor has a second coil and a third coil symmetrical to the second coil. When current is applied to the radio frequency filtering circuitry, the current in the second coil causes a first induced current in the first coil and the current in the third coil causes a second induced current in the first coil, wherein the second induced current is approximately equal in magnitude and opposite in direction to the first induced current. As such, the second induced current may compensate for the first induced current.

Inductor with embedded symmetric resonant circuit

An output circuit included in an integrated circuit may employ multiple protection circuits to protect driver devices from damage during an electrostatic discharge event. One protection circuit clamps a signal port to a ground supply node upon detection of the electrostatic discharge event. Another protection circuit increases the voltage level of a control terminal to one of the driver devices during the electrostatic discharge event to reduce the voltage across the driver device and prevent damage to the device.

Electrostatic discharge network for driver gate protection

To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).

Multi-core oscillator with transient supply voltage assisted mode switching

Embodiments disclosed herein relate to a low-voltage dropout regulator and more specifically to improving a power supply rejection ratio (PSRR) of the low dropout voltage regulator. The low dropout voltage regulator may be used to generate various voltages for integrated circuits of an electronic device. In some cases, a P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) voltage regulator may be used. However, the PMOS LDO may not provide a sufficient PSRR or reduction in supply noise. To address these issues, an N-type metal-oxide-semiconductor (NMOS) LDO voltage regulator having an NMOS pass transistor may be used. The NMOS LDO may provide a lower impedance than the PMOS LDO. Further, the NMOS LDO may provide an increased bandwidth and consume a smaller physical area than the PMOS LDO.

NMOS super source follower low dropout regulator

Growing community of inventors

Mountain View, CA, United States of America

Abbas Komijani