Siarc

Abbas El Gamel

In one embodiment of the invention, an inverter inverts an input signal and provides this inverted input signal into the base of an NPN bipolar transistor, acting as a pull-up device, whose collector is coupled to a positive power supply voltage. The input signal coupled to the input of the inverter is also coupled to the gate of a large N-channel MOSFET, acting as a pull-down device, having its drain coupled to the emitter of the bipolar transistor and its source coupled to ground. The common node of the bipolar transistor and the N-channel MOSFET provides the output signal of the driver. This driver uses much less area than a standard two-bipolar transistor BiCMOS driver with substantially equal performance. A small P-channel MOSFET having its gate connected to the input signal may be connected across the base and emitter of the bipolar transistor to provide a full output voltage at the output of the driver.

BiCMOS logic circuit for basic applications

An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-channel transistor. Each cell also comprises a high efficiency drive section containing a single bipolar pull-up transistor, a large N-channel pull-down transistor, and a small P-channel transistor. By using this cell, an extremely high compute capability per die area is achieved.

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Palo Alto, CA, United States of America

Abbas El Gamel