Texas Instruments Corporation

Abbas Ali

Qi-Zhong Hong

Dhishan Kande

Binghua Hu

Guruvayurappan Mathur

Poornika Fernandes

Henry Litzmann Edwards

Seetharaman Sridhar

Jarvis Benjamin Jacobs

Gregory Boyd Shinn

John Christopher Shriner

Christopher Scott Whitesell

Bhaskar Srinivasan

Alexei Sadovnikov

Hong Yang

Yunlong Liu

Scott William Jessen

Eric W Beach

Stefan Herzer

Rajni J Aggarwal

Young-Joon Park

Bradley David Sucher

Ming Yang

Yanbiao Pan

Thomas Edward Lillibridge

Bernard John Fischer

Chao Zuo

David William Hamann

Kyle McPherson

Yaping Chen

Sameer P Pendharkar

Brian Keith Kirkpatrick

Theodore Sidney Moise

Guoqiang Xing

Ming-Yeh Chuang

Tae S Kim

John P Erdeljac

Steven J Adler

Eugene C Davis

Sopa Chevacharoenkul

Steven Lee Prins

Kenneth Joseph Newton

Shariq Arshad

Shih Chang Chang

David Matthew Curran

Stephanie Leanne Hilbun

Byron Joseph Palla

Neil L Gardner

Erich Wesley Kinder

Britton Robbins

Can Duan

Ronald Chin

Scott Hiemke

Darrell R Krumme

Shih-Chang Chang

Joao Sergio Afonso

An integrated circuit includes a bipolar transistor extending into a [100] surface of a semiconductor substrate having a crystalline lattice. A deep trench surrounds the bipolar transistor and has a path having a plurality of sides. At least one side extends in a direction parallel to a <100> axis of the crystalline lattice.

Reduced silicon dislocation defects from deep SI trench integration

A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

Control of locos structure thickness without a mask

A microelectronic device includes an integrated deep trench in a substrate, with a field oxide layer on the substrate. The integrated deep trench includes a of deep trench extending into semiconductor material of the substrate, a deep trench sidewall dielectric layer contacting the substrate and an electrically conductive trench-fill material contacting the deep trench sidewall dielectric layer. The conductive trench-fill material is covered during the formation of the field oxide layer to minimize the trench-fill seam void volume. Minimizing the trench-fill seam void volume minimizes optical defectivity observed in subsequent yield enhancement. The integrated deep trench may be configured as a capacitor or may be configured as a contact to the underlying substrate.

Method of reducing integrated deep trench optically sensitive defectivity

A method of fabricating an integrated circuit includes forming and patterning a hardmask over a substrate such that the patterned hardmask exposes regions of the substrate. The exposed regions are etched, thereby forming trenches and a semiconductor fin between the trenches. Prior to removing the hardmask, a photoresist layer is formed and patterned, thereby exposing a section of the semiconductor fin. A dopant is implanted into the exposed section through the hardmask.

Implant blocking for a trench or FinFET without an additional mask

In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

Integrated circuits including composite dielectric layer

An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

Deep trench isolation with field oxide

Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.

Reduced semiconductor wafer bow and warpage

A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

Thin film resistor with punch-through vias

A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

IC with matched thin film resistors

An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.

IC with larger and smaller width contacts

A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

Semiconductor device with deep trench isolation and trench capacitor

A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.

Integrated trench capacitor with top plate having reduced voids

Growing community of inventors

Plano, TX, United States of America

Abbas Ali