Intel Corporation

Aashish Phansalkar

Youfeng Wu

Mauricio Breternitz, Jr

Peter Sassone

Balaji Vijayan

James Mason

A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.

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Austin, TX, United States of America

Aashish Phansalkar