Taiwan Semiconductor Manufacturing Comp. Ltd.

Aaron Wang

Fu-Jier Fan

Ho-Yin Yiu

Tsung-Yang Hung

Ruey-Yun Shiue

Yu-Jui Wu

Ming-Hsien Chen

Huang-Sheng Lin

Hsiang-Wei Wang

A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.

Method for wafer-level testing of integrated circuits

Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.

Top via pattern for bond pad structure

Growing community of inventors

Hsinchu, Taiwan

Aaron Wang