Globalfoundries U.S. Inc.

International Business Machines Corporation

Aaron Vallett

Qizhi Liu

Joseph R Greco

Robert F Vatter

Anthony K Stamper

John J Ellis-Monaghan

Steven M Shank

Michel J Abou-Khalil

Alvin Jose Joseph

Siva P Adusumilli

Rajendran Krishnasamy

Mark Levy

Randy Wolf

Sarah A McTaggart

Anupam Dutta

Bojidha Babu

Vvss Satyasuresh Choppalli

Disclosed is a semiconductor structure including a device (e.g., a field effect transistor (FET), a biosensor FET (bioFET) or an ion-sensitive FET (ISFET)) with a fluid-based gate. The structure includes a substrate, an intermediate layer on the substrate, and a semiconductor layer on the intermediate layer. The device includes, within the semiconductor layer, a source region, a drain region, and a channel region between the source and drain regions. The structure includes, for the fluid-base gate, a cavity within the intermediate layer below the channel region and lined with a dielectric liner. Optionally, the exposed surface of the dielectric liner within the cavity is functionalized. Additional dielectric layers are stacked on the semiconductor layer and at least one port extends essentially vertically through the dielectric layers, the semiconductor layer and the dielectric liner to the cavity so as to allow fluid for the fluid-based gate to flow into the cavity.

Field effect transistor with buried fluid-based gate and method

Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.

Field-effect transistors having a gate electrode positioned inside a substrate recess

The present disclosure relates to a semiconductor device including a substrate, a first region disposed in the substrate, a terminal region disposed in the first region, a body contact region disposed in the first region and spaced apart from the terminal region, a dielectric layer disposed on the substrate over the first region between the terminal region and the body contact region, an electrically conductive layer disposed on the dielectric layer, and a continuous metallic layer disposed on the electrically conductive layer and extending to the body contact region, the continuous metallic layer disposed on the body contact region and in physical contact with a top and side portions of the electrically conductive layer. The semiconductor device may additionally include a body contact interconnect disposed on a portion of the continuous metallic layer over the electrically conductive layer.

Semiconductor device including a body contact region and method of forming the same

Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

Semiconductor device structures with a substrate biasing scheme

Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.

Semiconductor structures including stacked depleted and high resistivity regions

The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.

Vertical field effect transistor (FET) with source and drain structures

Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

Vertical p-type, n-type, p-type (PNP) junction integrated circuit (IC) structure

Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure

Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

Method to build vertical PNP in a BiCMOS technology with improved speed

Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction.

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Jericho, VT, United States of America

Aaron Vallett