Intel Corporation

Hewlett-packard Development Company, L.p.

Aaron T Spink

Robert G Blankenship

Robert H Beers

David Stewart Dunning

Theodore Zale Schoenborn

Robert J Safranek

Naveen Cherukuri

Tim Frodsham

Rahul R Shah

Jeff Willey

Robert A Maddox

Debendra Das Sharma

Sanjay Dabral

Venkatraman Iyer

Arvind A Kumar

Raj K Ramanujan

Yen-Cheng Liu

Simon P Johnson

Herbert H Hum

Darren S Jue

Ashish Gupta

Vedaraman Geetha

Bahaa Fahim

Jeffrey Charles Swanson

Fulvio Spagna

Phanindra Mannava

Sitaraman V Iyer

William Harry Nale

Abhishek Das

Yuvraj S Dhillon

Jeffrey R Wilcox

Herbert H J Hum

Victor W Lee

Kenneth C Creta

Richard Eugene Kessler

Jasmin Ajanovic

Sridhar Muthrasanallur

Lance E Hacking

Steve Lang

Lakshminarayan Krishnamurty

David A J Webb, Jr

Sanjay Darbal

Maurice B Steinman

Allen Jay Baum

Selim Bilgin

Phanindra Mannaya

K Phanindra Mannava

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

High performance interconnect

A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined.

High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier

Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

Dynamically modulating link width

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

In one embodiment, the present invention includes a method for receiving a first portion of a first packet at a first agent and determining whether the first portion is an interleaved portion based on a value of an interleave indicator. The interleave indicator may be sent as part of the first portion. In such manner, interleaved packets may be sent within transmission of another packet, such as a lengthy data packet, providing improved processing capabilities. Other embodiments are described and claimed.

Interleaving data packets in a packet-based communication system

Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.

Write combining protocol between processors and chipsets

A predetermined network packet is utilized for power reduction in either or both of a transmitter and receiver when information is not needed. Upon detection of the predetermined network packet type, various portions of the transmitter and/or receiver may be clock gated or powered down.

Method, apparatus, and system for idle state definition for power management

Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

Methods and apparatuses to effect a variable-width link

Growing community of inventors

San Francisco, CA, United States of America

Aaron T Spink