Renesas Electronics America Inc.

Intersil Americas Inc.

Ami Semiconductor, Inc.

Zilker Labs, Inc.

Aaron Shreeve

Kenneth Wilson Fernald

Michael Jason Houston

Chun Cheung

Robert Thomas Grisamore

Mehul Dilip Shah

Riley Beck

Travis Guthrie

Narendra Kayathi

Demetri J Giannopoulos

Kiran Gonsalves

Kris Dehnel

Milton Martin Hood, Jr

Timothy William Nutt

Methods and systems for operating a voltage regulator are described. An apparatus may receive a feedback signal from a power stage. The feedback signal may be one of a sensed signal measured from an output of the power stage and a calibration signal representing a fixed voltage. The apparatus may convert the feedback signal into a correction signal. The apparatus may further adjust a synthetic current using the correction signal, the synthetic current being associated with the power stage.

System level offset calibration of multiphase voltage regulator

Systems, apparatuses, and methods for charging a bootstrap capacitor of a device during low power states are described. In an example, an apparatus can include a controller configured to enable a low power state of the device. The device can include a high side switching element and a low side switching element. The controller can, in response to the low power state of the device being enabled, operate the low side switching element of the device to charge the bootstrap capacitor of the device. The controller can, in response to the low power state of the device being enabled and a level of a control signal being a first level, activate the low side switching element to charge the bootstrap capacitor of the device.

Boot capacitor charge during low power states

A novel integrated switched mode power supply circuit that provides supply voltages to an integrated circuit may be of minimal complexity and have the capacity for a wide range of input supply voltages. The novel power supply may include cascaded, unregulated step-down charge pumps (e.g. unregulated voltage splitters), one or more linear regulators coupled to the output of the cascaded voltage splitters, and a start-up current source to provide the IC supply current until the input supply voltage is sufficiently high for the voltage splitter(s) to be functional to provide the IC supply current. Furthermore, each voltage splitter may be activated or disabled depending on the value of the input supply voltage, and the input of a disabled voltage splitter may be shorted to its output via an integrated power switch. Using (cascaded) voltage splitters to provide the IC supply current reduces overall power dissipation in the IC.

Integrated power supply with wide input supply voltage range

Embodiments of a system and method to control the overlap times&#x2014;and deadtime delays&#x2014;in power converters may support both overlapping and non-overlapping gate control signals, which may provide improved efficiency optimization across a wider range of applications. Various embodiments may be configured to provide careful partitioning between hardware implementation and software control, in order to better accommodate microprocessor-based power converters. Software algorithms may be used to avoid restrictions such as high gate impedance and changing load effects, and protection against errant operation may be provided using an overlap watchdog circuit. Various control circuits may be operated according to one or more algorithms configured to optimize both the HS-to-LS and LS-to-HS deadtime delays for obtaining minimum possible PWM duty cycle values to achieve improved power efficiency.

Method for control of overlap times in switching power converters

An operational amplifier with two differential pairs coupled to different current sources. The gate terminals of the transistors in the first differential pair are used as input terminals providing common mode input for most of the rail-to-rail voltage. The bulk terminals of the transistors in the second differential pair are used as input terminals providing common mode input for the remainder of the rail-to-rail voltage to thereby accomplish full rail-to-rail common mode. By using the bulk terminals of the field effect transistors in the second differential pair, rather than the gate terminals, as the input terminal, the operational amplifier may be constructing in a single well, thereby being compatible with standard digital CMOS processes. Alternatively, the bulk-driven transistors may be replaced with gate-driven depletion type transistors. The high voltage transistors in the output stage further reduce the offset voltage of the operational amplifier.

High voltage, low-offset operational amplifier with rail-to-rail common mode input range in a digital CMOS process

Growing community of inventors

Austin, TX, United States of America

Aaron Shreeve