Microsoft Technology Licensing, LLC

Aaron Sebastian Giles

Eric P Traut

Andrew Ernest Nicholas

Idan Avraham

Xiongjian Fu

Osama M Salem

Tim Carroll

James Norris Dieffenderfer

Thomas Andrew Sartorius

Michael Scott McIlvaine

Rene Antonio Vega

Parag Chakraborty

Clarence Siu Yeen Dang

Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a 'stack panic fault exception' that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

Providing exception stack management using stack panic fault exceptions in processor-based devices

A method includes determining that an operation should be performed to restore 80 bits stored in memory for an 80 bit register of a guest architecture on a host having 64-bit registers. The method further includes storing 64 bits from the 80 bits in a host register. The method further includes storing the remaining 16 bits from 80 bits in supplemental memory storage. The method further includes identifying a floating point operation that should be performed to operate on the 80-bit register for the guest architecture. As a result, the method further includes using the 64 bits in the host register and the remaining 16 bits stored in memory in a supplemental memory storage to translate a floating point number represented by the 80 bits to a 64-bit floating point number and store the 64-bit floating point number in the host register.

Efficient emulation of guest architecture instructions

Various mechanisms are disclosed herein for the saving and restoring of virtual machine environment state. For example, virtual machine state can be either be saved or (multiple) snapshots can be taken of the virtual machine state. In the latter case, virtual processors can be allowed to run while the memory of the virtual machine state is being saved. In either case, virtual devices associated with the virtual machine environment can be quiesced such that these devices can prepare themselves to be saved. Once such virtual devices and memory are saved, they can also be restored. For example, restoration of memory can occur while virtual processors are running at the same time. And, moreover, restoration can occur in batches of pages, thus optimizing the response time for restoring saved data.

Concurrent virtual machine snapshots and restore

Several embodiments of the present invention provide a means for improving data access security in computer systems to support high-security applications, and certain of these embodiments are specifically directed to providing sector-level encryption of a virtual hard disk in a virtual machine environment. More specifically, certain embodiments are directed to providing sector-level encryption by using plug-ins in a virtual machine environment, thereby providing improved data access security in a computer system that supports high-security applications. Certain embodiments also use encryption plug-ins associated with standard encryption software for exchanging data between a virtual machine (VM) and its associated virtual hard drive(s) (VHDs). Moreover, several embodiments of the present invention are directed to the use of plug-in encryption services that interface with, and provide services for, a VM via a VM Encryption API (or its equivalent).

Systems and methods for data encryption using plugins within virtual systems and subsystems

A method for emulating the functionality of VGA hardware, wherein the emulator program of the present invention maintains a set of tables that permits the emulator program to branch to a function customized for both the instruction and the operating mode of the VGA hardware. When the customized function has already been generated, the emulator will automatically dispatch directly into the customized function. If an instruction is executed at a time when the VGA operating mode has changed, the addresses of the customized functions are loaded from a second table. If a customized function is not present, a customized function is generated and the tables are updated to point to the addresses of the newly created customized function. As the VGA hardware is switching among operating modes, a customized function is not generated until such time when an actual instruction is executed for the VGA hardware.

Emulating the operation of a video graphics adapter

System and method for emulating the operation of a video graphics adapter

A method for processing software instructions in an emulated computing environment is provided in which instruction blocks from the application programs of a guest computer system are parsed to determine whether the instruction blocks include instructions executable at user level or supervisor level. Those instruction blocks that are executable at user level are passed directly to the processor of the host computer system, and those instruction blocks that are executable at supervisor level, are translated before being passed to the processor for execution. In the case of instruction blocks that include instruction blocks executable at supervisor level, prior to translation, a cache is queried to determine whether a translation for the instruction block is in the case. If a translation is in the cache, the translated version in the cache is provided to the processor for execution. If a translation is not in the cache, translation occurs, and the translated instruction block is saved to the cache.

Method for hybrid processing of software instructions of an emulated computer system

A method for performing a write operation to a hard drive or other memory space is provided. The hard drive is represented as at least two files. The first file is a parent drive and includes some content of the hard drive. Writes made to the hard drive are recorded in a second file, known as a differencing drive. Because no changes are made to the content of the parent drive, the content of the hard drive may be rolled back to the content of the parent drive by discarding the differencing drive.

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Issaquah, WA, United States of America

Aaron Sebastian Giles