Micron Technology Incorporated

Intel Corporation

Round Rock Research, LLC

Lodestar Licensing Group LLC

Aaron S Yip

Benjamin S Louie

Jin-Man Han

Mark Alan Helm

Hagop A Nazarian

Paolo Tessariol

Pranav Kalavade

Dzung Huu Nguyen

Ali Mohammadzadeh

Toru Tanzawa

Krishna Kumar Parat

Graham Richard Wolstenholme

Andrew Bicksler

Khaled Hasnat

Shafqat Ahmed

Kunal R Parekh

Hendrik Hartono

Jung Sheng Hoei

Tomoko Ogura Iwasaki

Dheeraj Srinivasan

Xiaojun Yu

Deepak Thimmegowda

Tomoharu Tanaka

Sivagnanam Parthasarathy

Akira Goda

Vishal Sarin

Mustafa Nazmi Kaynak

Patrick Robert Khayat

Theodore T Pekny

Qiang Tang

Ramin Ghodsi

Shigekazu Yamada

Chang Wan Ha

Yoshihiko Kamata

Hao Nguyen

Erwin E Yu

Lawrence Celso Miranda

Sheyang Ning

Yunqiu Wan

Dzung Nguyen

Yongna Li

Violante Moschiano

Tommaso Vali

Michele Piccardi

June Lee

Karl David Schuh

Shantanu R Rajwade

Umberto Siciliani

Daniel J Hubbard

Naveen Kaushik

Andrea Giovanni Xotta

Rohitkumar Makhija

Guido Luciano Rizzo

Control logic in a memory device causes a plurality of source control signals to be applied to a plurality of deintegrated source segments of a first block of a plurality of blocks of a memory array of a memory device to selectively activate a plurality of sub-blocks of the first block and programs a plurality of select gate devices in a plurality of logical select gate layers spanning the plurality of sub-blocks and positioned at a drain-side of the first block of the memory array with a threshold voltage pattern.

Sub-block definition in a memory device using segmented source plates

A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

Independent plane architecture in a memory device

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

3D memory device including shared select gate connections between memory blocks

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

Devices including stair step structures, and related memory devices and electronic systems

A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.

Block-on-block memory array architecture using bi-directional staircases

A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

Microelectronic devices including control logic regions

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

Reducing programming disturbance in memory devices

Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block, and causes a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.

Using non-segregated cells as drain-side select gates for sub-blocks in a memory device

A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

Microelectronic devices having a memory array region, a control logic region, and signal routing structures

Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

Memory devices with four data line bias levels

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block.

A memory device comprises a substrate and a memory array disposed above the substrate, the memory array comprising a plurality of vertically stacked layers, each vertically stacked layer comprising a plurality of word lines. The memory device further comprises a plurality of vertical string driver circuits disposed above the memory array, wherein each of the plurality of vertical string driver circuits comprises one or more semiconductor devices coupled to a respective one of the plurality of word lines.

Vertical string driver for memory array

A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.

Memory devices with user-defined tagging mechanism

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first pillar of a first memory cell string; a second pillar of a second memory cell string; a first conductive structure extending in a first direction, the first conductive structure located over and in electrical contact with the first pillar; a second conductive structure extending in the first direction, the second conductive structure located over and in electrical contact with the second pillar; a select gate coupled to the first and second memory cell strings; a first data line located on a first level of the apparatus and extending in a second direction, the first data line located over the first conductive structure and in electrical contact with the first conductive structure; and a second data line located on a second level of the apparatus and extending in the second direction, the second data line located over the second conductive structure and in electrical contact with the second conductive structure.

Memory device including data lines on multiple device levels

Growing community of inventors

Los Gatos, CA, United States of America

Aaron S Yip