Advanced Micro Devices Corporation

Aaron S Rogers

Daniel William Bailey

Bradley Gene Burgess

Eric C Quinnell

Aswin K Gunasekar

James Joseph Montanaro

Peter J Hannan

James J Montanaro

Roger D Pannell

Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Pipeline power gating

A semiconductor device includes a primary voltage rail, a secondary voltage rail, a plurality of transistors coupled between the primary and secondary voltage rails, and control logic operable to enable a first subset of the plurality of transistors to couple the primary voltage rail to the secondary voltage rail. During a steady state condition, the first subset comprises less than all of the plurality of transistors.

Variable-width power gating module

A method, electronic device, and system are provided in which data is stored in a gateable retention storage element. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus which includes a silicon chip. The method includes storing a data value in a storage element, wherein the storage element is at least one of a flip-flop, a latch or a register. The method also includes placing the storage element in a low power state comprising removing one or more existing connections between the actual ground node and at least one other component in the storage element. The method also includes maintaining the data value in the storage element subsequent to placing the storage element into the low power state. The electronic device includes a storage component for storing a data value. The electronic device also includes a pair of cross-coupled inverter components communicatively coupled to the storage component, the pair of cross-coupled inverter components being adapted to maintain the data value stored by the storage component subsequent to placing the storage component into a low power state and being adapted to maintain a connection with an actual ground node subsequent to placing the storage component into the low power state. The system includes an array of storage elements adapted to store data.

Power gateable retention storage element

To determine performance degradation at functional module in a normal power state due to a power control device, voltages are applied to oscillators at a power diagnostic module. A first voltage is a supply voltage for the data processing device, and a second voltage is a supply voltage applied at a functional module of the data processing device. Counters are adjusted based on the oscillators to determine the oscillators' respective frequencies. In addition, the power diagnostic module can include a timer to measure the length of time that the functional module is in a low-power state, and an analog to digital converter to measure the voltage applied to the functional module during transitions to and from the low-power state.

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Pflugerville, TX, United States of America

Aaron S Rogers