Micron Technology Incorporated

Mircon Technology, Inc.

Aaron Preston Boehm

Scott E Schaefer

Glen Earl Hush

Fa-Long Luo

Scott D Van De Graaff

Mark D Ingram

Todd Jackson Plum

Debra M Bell

Steffen Buch

Lance W Dover

Kristen M Hopper

Erika Prosser

Melissa I Uribe

Jongtae Kwak

Jeffrey P Wright

Jeremy Chritz

Tamara Schmitz

George Edward Pax

Matthew Alan Prather

David Hulton

Max Vohra

Hui Fu

Methods, systems, and devices for persistent health monitoring for volatile memory devices are described. A memory device may determine that an operating condition associated with an array of memory cells on the device, such as a temperature, current, voltage, or other metric of health status is outside of a range associated with a risk of device degradation. The memory device may monitor a duration over which the operating condition is outside of the range, and may determine whether the duration satisfies a threshold. In some cases, the memory device may store an indication of when (e.g., each time) the duration satisfied the threshold. The memory device may store the one or more indications in one or more non-volatile storage elements, such as fuses, which may enable the memory device to maintain a persistent indication of a cumulative duration over which the memory device is operated with operating conditions outside of the range.

Persistent health monitoring for volatile memory systems

Apparatuses, systems, and methods related to a data center using a memory pool between selected memory resources are described. A data center using a memory pool between selected memory resources may enable performance of functions, including automated functions critical for prevention of damage to product, personal safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, a method described herein includes transmitting, from a processor at a first vehicle that comprises the processor and memory, a request to access a pool of memory resources configured from a plurality of vehicles each having a local processor and memory, receiving, from a second vehicle of the plurality of vehicles, an indication to access the pool of memory resources, and reading data from or writing data to the memory at the second vehicle using the processor at the first vehicle based at least in part on receiving the indication to access the pool of memory resources.

Data center using a memory pool between selected memory resources

Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

Techniques for detecting a state of a bus

Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

Error correction memory device with fast data access

Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

Host verification for a memory device

Methods, systems, and devices for verification of a volatile memory, such as a dynamic random-access memory (DRAM), using a unique identifier (ID) are described. A memory device may store a unique ID for a DRAM component of the memory device in non-volatile memory (e.g., in the DRAM, external to the DRAM). A host device coupled with the memory device may store, to non-volatile memory at the host device, information for verifying the identity of the DRAM component, for example, based on the unique ID. The memory device and host device may perform a procedure for verification of the identity of the DRAM component using the unique ID of the DRAM and the verification information stored at the host device. If the host device detects that the DRAM has been replaced or modified based on the verification procedure, the host device may disable one or more features of the memory device.

Verification of a volatile memory using a unique identifier

Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.

Methods and devices for error correction

Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.

Memory command verification

Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.

Apparatuses and methods for ordering bits in a memory device

Methods, systems, and devices for evaluation of memory device health monitoring logic are described. A memory device may include health monitoring logic that is operable to be enabled in a configuration that corresponds to an output, such as an expected output, regardless of a degradation level of the memory device. Such a configuration may be enabled in a mode, such as a test mode, during which the memory device, or a host device coupled with the memory device, or some combination, may evaluate a difference between the output and an actual output of the health monitoring logic. The actual output being the same as the output may provide an indication that at least a portion of the health monitoring logic is functioning properly, and the actual output being different than the output may provide an indication that at least a portion of the health monitoring logic is not functioning properly.

Evaluation of memory device health monitoring logic

Methods, systems, and devices for inter-device communications for memory health monitoring are described. These communications relate to a host device that is associated with a memory device that monitors and reports health information (e.g., one or more parameters associated with a status of the memory device). The memory device may transmit the health information to the host device (e.g., a vehicle or a computer of the vehicle), which may perform one or more operations and transmit the health information to another entity of a system (e.g., ecosystem) including the host device. The host device may additionally or alternatively use the health information. In some cases, the other entity may receive the health information and transmit a signal back to the host device based on the health information. The other entity of the ecosystem may receive the health information and may make a determination based on the health information.

Inter-device communications for memory health monitoring

Methods, systems, and devices for operating frequency monitoring for memory devices are described for monitoring one or more operating frequency ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more operating frequency ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.

Frequency monitoring for memory devices

Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.

Memory device with status feedback for error correction

Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

Apparatuses and methods for organizing data in a memory device

Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

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Boise, ID, United States of America

Aaron Preston Boehm