Infineon Technologies Ag

Qimonda Ag

Aaron Nygren

Thomas Hein

Georg Braun

Patrick Heyne

Bret A Johnson

Andreas T&auml;uber

Andreas Täuber

Eckehard Pl&auml;ttner

An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.

Integrated semiconductor memory with determination of a chip temperature

A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of phase detector cells and a control unit. The delay locked loop delays an input signal by a delay time via the delay chain depending on the number of delay cells in the series that are activated for delay. The phase detector arrangement detects the phase of the signal at the output of each delay cell in the delay chain. The control unit activates a number Z of the delay cells of the delay chain based on the difference in phase of the original signal and the delayed signal.

Delay locked loop and method for setting a delay chain

A driver system, a driver calibration circuit arrangement for calibration of an impedance of a driver circuit arrangement, and a method for calibration of an impedance of a driver circuit arrangement can achieve improved driver behavior, with respect to undesirable distortions of the slew rate caused by off-chip drivers of DDR memory modules. A driver system has a first driver part with at least one variable impedance by which an operating point of the first driver part is determined with respect to a first potential and a second potential. The potentials supply the first driver part. A first monitoring device adjusts an impedance value of the variable impedance such that the operating point differs from a mid-point of the first and of the second potential.

Pseudodynamic off-chip driver calibration

The invention relates to a method and an apparatus for producing a reference voltage that is applied to reference voltage inputs on receiver units in order to discriminate between the logic states of a data signal that is transmitted to a receiver end. A transmission device transmits, in addition to the data signal, a clock signal to the receiver end. The receiver end has, on the output side of a receiver unit that receives the clock signal, an integrator that integrates the clock signal and produces the reference voltage from the integrated value.

Method and apparatus for producing a reference voltage

A calibration configuration for setting an adjustable impedance has a voltage divider with a variable resistor and a resistor connected in series, which circuit is supplied with potentials of a supply voltage and has, between the resistors, a partial voltage tap off terminal. A circuit has a further resistor, whose value is in a fixed relationship with a resistance of the first voltage divider resistor, and generates a voltage dependent upon a value derived from the further resistor. The voltage and the partial voltage are fed to a comparator for outputting a comparison result to a downstream control logic unit, which logic unit is coupled to the resistor of the first voltage divider and generates a control signal dependent upon the comparator output signal. The control logic unit control signal is used to set the variable resistor until the voltages fed to the comparator correspond to one another.

Calibration configuration

A buffer device includes a plurality of latch stages which each have a latch device and a multiplexer. At least the multiplexer of the first latch stage on the output side is associated with a feedback loop of the latch device of this latch stage. The feedback loop is provided for data buffering. The buffer device keeps a data output on an output line stable.

Buffer device

A system for bidirectional signal transmission of an electrical signal from a transmitter at a first location to a receiver at a second location, and from a transmitter at the second location to a receiver at the first location via a common transmission line forms, with each receiver, a line termination for matching the received electrical signal. Each transmitter is in the form of a combined transmission/termination circuit configuration which may in each case be operated in a transmission operating mode and in a reception/termination operating mode. A control circuit produces an operating mode control signal. Each transmission/termination circuit configuration is configured such that it can be switched either to the transmission operating mode or to the reception/termination operating mode depending on the operating mode control signal which is supplied from the control circuit. A method for bidirectional signal transmission of an electrical signal is also provided.

Method and system for bidirectional signal transmission

A method and a device generate a reference voltage for discriminating between the logic states of a data signal received at a receiving end. A transmitting device transmits a continuous clock signal with a constant pulse period duration and a symmetrical sequence of low and high clock signal states in such a way that, at the receiver end, the clock signal has the same low and high voltage levels as the received data signal and it is subject to the same system-governed variations as the received data signal. An integrator at the receiver end receives and integrates the clock signal, and the integrated value becomes the reference voltage for the receiver unit.

Method and device for generating a reference voltage

A method is provided for generating a data strobe signal in order to transmit the latter through a signal line with tristate behavior from/to a semiconductor memory module for writing/reading data to/from the semiconductor module. The data strobe signal, in response to the outputting or the reception of a read/write command, proceeding from the tristate state, is clocked with a predetermined clock frequency after a short preamble period. The data strobe signal is occupied, in the preamble period, by one or more pulses corresponding to the clock frequency. In very fast memory systems, this avoids a temporal offset between a system clock and data acceptance controlled by data strobe signal pulses. A semiconductor circuit configuration having a semiconductor circuit module with a circuit for generating such a data strobe signal, is also provided.

Method and circuit configuration for generating a data strobe signal for very fast semiconductor memory systems

A communications method is described in which two memory modules receive data and commands from a controller module via a common data and command bus. The memory modules contain active line terminations. By a second chip select input, one of the memory modules can monitor the write commands that pass from the controller module to the other memory module, and thus activate the line terminal in the monitoring memory module.

Method for data communication between a plurality of semiconductor modules and a controller module and semiconductor module configured for that purpose

The bus system has a bus and a plurality of line sections connected to the bus via respective drivers. The bus with line sections that are not needed can be interrupted at optional break points.

Bus system

The electrical circuit includes a plurality of circuit components which are connected via a bus. At least one of the circuit components can be tested independently of the other circuit components. The circuit component which is to be tested and the method for testing the circuit component are distinguished in that steps are taken to ensure that, during testing, the circuit component which is tested, outputs no data to the bus, and/or instead of the data which would need to be output to the bus during normal operation, outputs other data to the bus.

Electrical circuit and method for testing a circuit component of the electrical circuit

A redundant multiplexer, in which the addresses of two series-connected switches are compared, and the switches are possibly interchanged, to ensure that no faulty bit lines are read. The redundant multiplexer is used in a semiconductor memory configuration having redundant bit lines for replacing faulty bit lines. The redundant bit line received control and switching signals to determine which of the bit lines are to be replaced.

Redundant multiplexer for a semiconductor memory configuration

In the redundancy multiplexer for a semiconductor memory configuration control or switching signals are passed to multiplexer areas only via &frac14; of the interface width. This reduces the propagation time for the signals by a factor of 3.

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Munich, Germany

Aaron Nygren