Cadence Design Systems, Inc.

Aaron Mitchell Spratt

Chandrashekar Lakshminarayanan Chetput

William Scott Cranston

Abhijeet S Kolpekwar

Rajat Kanti Mitra

Nan Zhang

Dan Richard Kaiser

Junwei Hou

Joseph Leo Zielke, Jr

The present disclosure relates to a computer-implemented method for mixed signal design verification. Embodiments may include receiving, using a processor, an electronic circuit design and compiling and elaborating the electronic circuit design. Embodiments may also include simulating the electronic circuit design and updating, during the simulating, a System Verilog User-Defined Resolution function ('SV-UDR') associated with the electronic circuit design.

System, method, and computer program product for mixed signal verification

The present disclosure relates to a computer-implemented method for simulating a circuit design having a discrete domain segment connected to a continuous domain segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the discrete domain segment and the continuous domain segment. The method may also include splitting the discrete domain segment into a plurality of transistor network models to provide for bi-directional transfer of data between the continuous domain segment and the discrete domain segment, wherein at least one of the plurality of transistor network models utilizes only one or more drivers external to a module.

System, method, and computer program product for generating bidirectional real number models in an electronic design

Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.

Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language

The present disclosure relates to a computer-implemented method for simulating an analog and mixed-signal circuit design having a digital circuit segment connected to an analog circuit segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the digital circuit segment and the analog circuit segment. The method may further include splitting the digital circuit segment into a plurality of transistor network models to provide for bidirectional transfer of data between the analog circuit segment and the digital circuit segment.

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Milford, MA, United States of America

Aaron Mitchell Spratt