Alcatel Lucent

Aaron Maxwell MacDonald

James Michael Schriel

Richard Grieve

Dion Pike

Jason T Sterne

Robert John Johnson

Tim White

Sean Donald Robert Code

A system and method are provided for implementing CESOP inexpensively yet effectively implemented across an MPLS or an IP network. A Zarlink chip provides CESOP functionality, providing a TDM pseudowire by converting TDM streams into Ethernet packets. These Ethernet packets can be processed by a Marvell chip, which has the ability to perform QoS functions on the packets. The Marvell chip converts the Ethernet packets into MPLS or IP packets for transmission over a packet network. Use of a single virtual circuit label, invisible to the packet network for routing purposes, within the Ethernet packet allows Marvell chips at each end of the emulated circuit to tie traffic to a particular customer and to thereby apply appropriate QoS constraints.

Interworking circuit emulation service over packet and IP/MPLS packet processing

A method for incorporating a queuing device as a lossless processing stage in a network device in a communications network, comprising: monitoring a depth of a queue in the queuing device, the queue for receiving packets from an upstream device within the network device, the queuing device acting as a discard point by discarding packets when the queue is full; and, if the depth passes a predetermined threshold, sending a message to the upstream device to reduce a rate at which packets are sent to the queuing device to prevent the queue from filling and thereby preventing packet discarding and loss by the queuing device.

Method and system for using a queuing device as a lossless stage in a network device in a communications network

A method and apparatus are provided for scheduling tasks within a computing device such as a communication switch. When a task is to be scheduled, other tasks in the work queue are analyzed to see if any can be executed simultaneously with the task to be scheduled. If so, the two tasks are combined to form a combined task, and the combined task is placed within the job queue. In addition, if the computing device has insufficient resources to execute the task to be scheduled, the task is placed back into the work queue for future scheduling. This is done in a way which avoids immediate reselection of the task for scheduling. Task processing efficiency is increased, since combining tasks reduces the waiting time for lower priority tasks, and tasks for which there are insufficient resources are delayed only a short while before a new scheduling attempt, rather than rejecting the task altogether.

Intelligent scheduler for multi-level exhaustive scheduling

A method and apparatus are provided for storing the boot configuration PROM of a microprocessor in an FPGA. The boot interface of the microprocessor, such as an I2C interface, leads to the FPGA instead of to a PROM. The boot configuration is stored as an image in the FPGA, and the microprocessor accesses the boot configuration using its normal boot interface. In this way, a dedicated boot PROM is not needed, saving real estate on the card on which the microprocessor is located. The boot configuration is also more easily modified, such as for version upgrades or diagnostics, than if the boot configuration were stored on a dedicated PROM. Different boot configurations may be stored as software images on a separate housekeeper processor, for loading into the FPGA.

Growing community of inventors

Ottawa, Canada

Aaron Maxwell MacDonald