Micron Technology Incorporated

Round Rock Research, LLC

Other

Aaron M Schoenfeld

Jerry Michael Brooks

David R Cuthbert

Mark T Van Horn

Richard N Hedden

Tyler J Gomm

R Jacob Baker

Wen Qian Li

Ross E Dermott

David J Corisis

Vladimir Mikhalev

Manny K Ma

James E Miller, Jr

Daniel B Penney

Alan John Wilson

William Chad Waldrop

Larry Duane Kinsman

Timothy J Allen

J Mike Brooks

Manny K F Ma

Timothy B Cowles

Debra M Bell

Greg A Blodgett

Gordon D Roberts

Jeffrey D Bruce

Manny Kin F Ma

Rajesh Somasekharan

Travis E Dirkes

Wallace E Fister

Russell J Baker

An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Method and apparatus for providing symmetrical output data for a double data rate DRAM

A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.

Circuit and method for controlling a clock synchronizing circuit for low power refresh operation

A method and apparatus are provided for substantially reducing or eliminating the timing skew caused by delay elements in a delay locked loop. A method and apparatus are disclosed wherein a rising edge of a local timing signal is established and phase-locked to a rising edge of a system clock signal by delaying the system clock signal. A falling edge of the local timing signal is established and phase-locked to a falling edge of the system clock signal by further delaying only a portion of a signal representative of the delayed clock signal. By separately delaying different portions of the system clock signal and using the separately delayed portions to establish a local timing signal, a local timing signal may be established which is compensated for the varied effects of delay elements in a delay locked loop.

Method and apparatus for output data synchronization with system clock in DDR

A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs for further reducing the power to portions of the memory device.

Circuit and method for reducing power in a memory device during standby modes

A system unit including a processor unit and an input storage unit. The processor unit generates an input signal and a clock signal. The input storage unit receives the input signal and the clock signal. The input storage unit processes the clock signal to generate an input buffer enable signal. The input buffer enable signal changes from an inactive state to an active state a short time interval before at least one of the transitions of the clock signal. A method includes receiving a clock signal having a plurality of transitions at an input buffer unit, enabling the input buffer unit before each of the plurality of transitions, and disabling the input buffer unit after each of the plurality of transitions.

Method and unit for buffer control

A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs further reducing the power to portions of the memory device.

A method and apparatus for decoupling conductive portions of a microelectronic device package. In one embodiment, the package can include a microelectronic substrate and a conductive member positioned at least proximate to the microelectronic substrate. The conductive member can have first and second neighboring conductive portions with at least a part of the first conductive portions spaced apart from a part of the neighboring second conductive portion to define an intermediate region between the first and second conductive portions. Each conductive portion has a bond region electrically coupled to the microelectronic substrate. A dielectric material is positioned adjacent to the first and second conductive portions in the intermediate region and has a dielectric constant of less than about 3.5.

Method and apparatus for decoupling conductive portions of a microelectronic device package

Apparatus is provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffered clock signal and generates a delayed clock signal, and an output circuit including output signal paths for outputting the output signals synchronously with the system clock signal by using the delayed clock signal. At least one of the output signal paths includes a delay circuit and an output buffer. Each delay circuit provides a programmable delay to the delayed clock signal to generate a unique delayed clock signal used to clock an output signal into the respective output buffer. By programming the delays based upon output skew, the output skew can be improved.

Method and apparatus for improving output skew for synchronous integrated circuits

A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or input/output configuration

Device, system and method for reducing power in a memory device during standby modes

Growing community of inventors

Boise, ID, United States of America

Aaron M Schoenfeld