Sandisk Technologies Inc.

Spansion Llc.

Google Inc.

Robert Boschgmbh

Gray Company

Western Digital Technologies, Inc.

Samsung Electronics Co., Ltd.

Cypress Semiconductor Corporation

Aaron Lee

Mrinal Kochar

Nian Niles Yang

Guowei Wang

Abhijeet Bhalerao

Abhijeet Manohar

Yonggang Wu

Mikhail Palityka

Sachit Chandra

Christian Oestlien

Jorge Emilio Nagel

Yew Yin Ng

Paul Trepagnier

Powell Kinney

Matthew Taylor Dooner

Michael Thomas Dewenter

Ivan Baran

Neil Traft

Sergey Drakunov

Nancy S Leong

Hauke Schmidt

Dennis S Ea

Cynthia Hua-Ling Hsu

Tuolin Chen

Deepanshu Dutta

Xiang Yang

Gerrit Jan Hemink

Ken Oowada

Christopher Richard Uhlik

Chris Avila

Monika Hildegard Henzinger

Toru Miwa

Hua-Ling Cynthia Hsu

David Marwood

Jasson Schrock

John Piscitello

Nikhil Vijay Chandhok

Mahim Raj Gupta

Steve Okamoto

Hounien Chen

Gunthar Hartwig

Jiani Zhang

Peter C Chane

Matthew Vosburgh

Shahid Choudhry

Rohan Dhekane

Jian Feng Chen

Zhenming Zhou

Dana Lee

Jianmin Huang

Steven Theodore Sprouse

Johnny C Chen

Darlene G Hamilton

Binh Quang Le

Gautam Ashok Dusija

Niles Yang

Christopher A Peri

Sahil Sharma

Deepak Raghu

Rohit Sehgal

Chun Sum Yeung

YenLung Li

Tiao-Hua Kuo

Michael A VanBuskirk

Gulzar Ahmed Kathawala

Vimal Kumar Jain

Peter Chang King

Wei Daisy Cai

Yong Huang

Yi-Chieh Chen

Fan Wan Lai

Anne Pao-Ling Koh

Xiang Sun

Derek McAuley

Anne Koh

Neil Michael Traft

Paul Gerald Trepagnier

Nancy Leong

Johnny Chen

Toulin Chen

Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.

Non-volatile storage system with program execution decoupled from dataload

Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

Concurrent programming of multiple cells for non-volatile memory devices

Apparatuses and techniques are described for reliably storing bad column data in a memory device. Units of bad column data and related units of error detection data are stored in non-adjacent groups of memory cells connected to a word line in a ROM block. A unit of bad column data and a related unit of error detection data can be stored in respective groups of memory cells which are relatively far apart from one another along the word line. This helps ensure that a defect in some NAND strings will not affect both the unit of bad column data and a related unit of error detection data. In another aspect, a unit of bad column data and a related unit of error detection data can be stored using different input/output circuits to further increase robustness.

Robust storage of bad column data and parity bits on word line

Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die, the programming operation including populating a transfer data latch with a first set of data and transferring the data to a first data latch, populating the transfer data latch with a second set of data and transferring the data to second data latch, arranging the first and second data sets in a suitable format of the multi-state block, and writing the data sets to the multi-state block; prior to populating the transfer data latch with the second data set, performing a program suspend and read operation thereby populating the transfer data latch with read data; and comparing the read data to the data contained in the first data latch and, if the comparison results in a match, identifying the subject die as faulty.

System countermeasure for read operation during TLC program suspend causing ADL data reset with XDL data

Detecting a faulty memory block. Various methods include: performing a read operation on a memory block of the memory array, the read operation generates a failed bit count; determining the failed bit count in above a value associated with an overall failed bit count; determining the failed bit count is above a threshold value; in response, performing a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, the confirmation process results in erase pass or erase fail; and marking the memory block for garbage collection in response to determining the confirmation process results in erase fail. Methods additionally include setting the level of the erase cycle by modifying at least one selected form the group comprising: an erase voltage parameter; an erase verify parameter; and a number of bits ignored during the erase cycle.

Detecting a faulty memory block

Systems, methods, and computer readable media are provided for automatically personalizing virtual reality content ratings using biometric data on a head-mountable display (HMD) device. A server includes a transceiver configured to transmit and receive data to and from a first electronic device, a memory, and at least one processor operably connected to the memory and the transceiver. The processor(s) is configured to receive application data and biometric data, wherein the biometric data corresponds to the application data from the first electronic device, generate a rating for an application related to the application data, wherein the generated rating is based on the biometric data, and store the generated rating to a database corresponding to the application in an online store.

System and method for virtual reality content rating using biometric data

A method for writing data to a NAND flash memory is disclosed, having steps of writing a first set of data to a first memory block, writing a second set of data to a second memory block, writing a third set of data to a third memory block and writing a fourth set of data to a XNOR memory block.

Methods and operations using XNOR functions with flash devices and solid state drives

Apparatuses, systems, methods, and computer program products are disclosed for changing storage parameters. An integrated circuit (IC) memory element receives a command to change a value of a parameter associated with the IC memory element. A parameter includes a setting for one or more storage operations of an IC memory element. An IC memory element receives one or more data sets with a command. A data set includes an identifier associated with a parameter to be changed and a new value for the parameter. Each of one or more data sets is received at a same data rate as a command. An IC memory element writes, for each of one or more data sets, a new value for a parameter to a storage location associated with the parameter.

Changing storage parameters

A system and method for operating a memory system includes receiving a first user data, writing the first user data to a first buffer, writing the first user data from the first buffer to a first selected memory location, writing the first user data from the first buffer into a second buffer when the first user data was successfully written to the first selected memory location. Data is retrieved from the first selected memory location and written into the first buffer. Data in the first buffer can be matched to the user data in the second buffer to confirm a successful storage of the first user data in the memory system. A previously stored user data can be retrieved from a third selected memory location and written into a third buffer when the previously stored user data was stored in the memory system before the first user data.

System, method and apparatus for preventing data loss due to memory defects using latches

Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Write abort detection for multi-state memories

Data that is initially stored in Single Level Cell (SLC) blocks is subsequently copied (folded) to a Multi Level Cell (MLC) block where the data is stored in MLC format, the data copied in a minimum unit of a fold-set, the MLC block including a plurality of separately-selectable sets of NAND strings, data of an individual fold-set copied exclusively to two or more word lines of an individual separately-selectable set of NAND strings in the MLC block.

Data folding in 3D nonvolatile memory

When the number of bad columns in a memory or plane is less than a threshold number then a first Error Correction Code (ECC) scheme encodes user data in first pages of a first size. If the number of bad columns is greater than the threshold number then a second ECC scheme encodes the user data in second pages of a second size that is smaller than the first size.

Bad column management in nonvolatile memory

Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.

Partially-bad block operation in 3-D nonvolatile memory

Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.

Non-volatile memory systems with multi-write direction memory units

Growing community of inventors

Mountain View, CA, United States of America

Aaron Lee