Micron Technology Incorporated

Semiconductor Components Industries, LLC

Aaron Kenneth Belsher

Jordan D Greenlee

John Mark Meldrim

Yi Hu

Dave Pratt

Raju Ahmed

Frank Speetjens

Tao D Nguyen

Darin Miller

Yung-Ta Sung

Siva Naga Sandeep Chalamalasetty

Allen R Gibson

Peter Rupert Barabash Barr

Giovanni Deamicis

Ulrich C Boettiger

Swarnal Borthakur

Richard A Mauritzson

Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

Conductive interconnects and methods of forming conductive interconnects

Some embodiments include an integrated assembly having an insulative mass over a conductive base structure. A conductive interconnect extends through the insulative mass to an upper surface of the conductive base structure. The conductive interconnect includes a conductive liner extending around an outer lateral periphery of the interconnect. The conductive liner includes nitrogen in combination with a first metal. A container-shaped conductive structure is laterally surrounded by the conductive liner. The container-shaped conductive structure includes a second metal. A conductive plug is within the container-shaped conductive structure. Some embodiments include methods of forming conductive interconnects within integrated assemblies.

Conductive interconnects suitable for utilization in integrated assemblies, and methods of forming conductive interconnects

An image sensor such as a backside illumination image sensor may be provided with analog circuitry, digital circuitry, and an image pixel array on a semiconductor substrate. Trench isolation structures may separate the analog circuitry from the digital circuitry on the substrate. The trench isolation structures may be formed from dielectric-filled trenches in the substrate that isolate the portion of the substrate having the analog circuitry from the portion of the substrate having the digital circuitry. The trench isolation structures may prevent digital circuit operations such as switching operations from negatively affecting the performance of the analog circuitry. Additional trench isolation structures may be interposed between portions of the substrate on which bond pads are formed and other portions of the substrate to prevent capacitive coupling between the bond pad structures and the substrate, thereby enhancing the high frequency operations of the image sensor.

Imaging systems with backside isolation trenches

A backside illuminated image sensor with an array of pixels formed in a substrate is provided. To improve surface planarity, bond pads formed at the periphery of the array of pixels may be recessed into a back surface of the substrate. The bond pads may be recessed into a semiconductor layer of the substrate, may be recessed into a window in the semiconductor layer, or may be recessed in a passivation layer and covered with non-conductive material such as resin. In order to further improve surface planarity, a window may be formed in the semiconductor layer at the periphery of the array of pixels, or scribe region, over alignment structures. By providing an image sensor with improved surface planarity, device yield and time-to-market may be improved, and window framing defects and microlens/color filter non-uniformity may be reduced.

Image sensors with improved surface planarity

Growing community of inventors

Boise, ID, United States of America

Aaron Kenneth Belsher