Sandisk Enterprise IP LLC

Sandisk Technologies Inc.

International Business Machines Corporation

Pliant Technology, Inc.

Fujitsu Corporation

Aaron Keith Olbrich

Douglas Alan Prins

Jack Frayer

Doug Prins

Robert W Ellis

Steven Theodore Sprouse

Johann George

Neil Richard Darragh

Sergey Anatolievich Gorobets

James M Higgins

Anand Kulkarni

Navneeth Kankani

Senthil Thangaraj

Divya Reddy

Yan Li

James Fitzpatrick

Chang Hua Siau

Manuel Antonio d'Abreu

Brian Walter O'Krafka

Alon Marcu

Xinde Hu

Grishma Shah

Darpan Dinker

Yacov Duzly

Farookh Moogat

Gopinath Balakrishnan

Paul Roger Stonelake

Vidyabhushan Mohan

Huapeng G Guan

Sainath Viswasarai

Yipei Yu

Koji Yoneyama

Anantharaj Thalaimalai Vanaraj

Yuichi Hirao

Evgeny H Firsov

Patrick Chiu

Yale Yueh Ma

Shigeru Hatakeyama

Graeme Weston-Lewis

Graeme Moffat Weston-Lewis

Neil R Darragh

Jack Edward Frayer

Systems and methods for increasing performance and reducing power consumption of a non-volatile memory system while the system acquires status information from a plurality of memory die are described. The non-volatile memory system may include a plurality of memory die and a system controller for controlling operations performed by each memory die of the plurality of memory die (e.g., read operations, write operations, or erase operations). The system controller may transmit or broadcast a first status command to each memory die of the plurality of memory die and in response simultaneously or concurrently receive one or more sets of status information from each memory die of the plurality of memory die. The status information may include ready/busy status information (e.g., indicating that a memory die is able to receive new data), programming loop count information, and erase loop count information.

Multi-die rolling status mode for non-volatile storage

Systems and methods disclosed herein allow for efficiently managing unmapped blocks to extend life of solid-state drives. In one aspect, a method includes: determining a quantity of unmapped storage units in the storage device and operating the storage device in a first mode of operation while the quantity satisfies a first threshold. The method also includes: changing to a second mode of operation if the quantity of unmapped storage units doesn't satisfy the first threshold. While operating in the second mode of operation, the method includes: determining whether processing a write command would reduce the quantity of unmapped storage units to a quantity less than a second threshold. If processing the write command wouldn't reduce the quantity of unmapped storage units to a quantity less than the second threshold, the method includes: accepting and processing the write command. Else, the method includes: forgoing acceptance and processing of the write command.

Efficiently managing unmapped blocks to extend life of solid state drive

Systems and methods disclosed herein allow for efficiently managing unmapped blocks to extend life of solid-state drives. In one aspect, a method includes: measuring a level of over-provisioning ('OP') in a storage device and operating it in a first mode of operation while the OP satisfies a first threshold. The method also includes: changing to a second mode of operation if the OP does not satisfy the first threshold. While operating in the second mode of operation, the method includes: (i) determining an unmapped portion of a declared storage capacity of the storage device; and (ii) determining whether processing a write command would reduce the unmapped portion to less than a second threshold. If processing the write command wouldn't reduce the unmapped portion to less than the second threshold, the method includes: accepting and processing the write command. Else, the method includes: forgoing acceptance and processing of the write command.

Efficiently managing unmapped blocks to extend life of solid state drive with low over-provisioning

A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.

Method and system for dynamic word line based configuration of a three-dimensional memory device

The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Method for modifying device-specific variable error correction settings

Systems, methods and/or devices are used to enable tracking intermix of writes and un-map commands across power cycles. In one aspect, the method includes (1) receiving, at a storage device, a plurality of commands from a host, the storage device including non-volatile memory, (2) maintaining a log corresponding to write commands and un-map commands from the host, (3) maintaining a mapping table in volatile memory, the mapping table used to translate logical addresses to physical addresses, (4) saving the mapping table, on a scheduled basis that is independent of the un-map commands, to the non-volatile memory of the storage device, (5) saving the log to the non-volatile memory, and (6) upon power up of the storage device, rebuilding the mapping table from the saved mapping table in the non-volatile memory of the storage device and from the saved log in the non-volatile memory of the storage device.

Tracking intermix of writes and un-map commands across power cycles

The embodiments described herein are methods and systems to enhance the reliability and performance of a persistent datastore (e.g., non-volatile memory such as flash memory). The method includes generating a log entry associated with first write data. The method also includes generating a first record including the log entry, the first write data, and pointer to a second record different from the first record. The method further includes performing a single write operation that includes writing the first record to the persistent datastore.

Method and system for forward reference logging in a persistent datastore

A memory controller receives a command to perform a memory operation, the command including a data packet comprising a plurality of data divisions. In response to receiving the command, for each individual memory device, the memory controller assigns to the individual memory device a respective data division, the respective data division including a plurality of data segments, and determines a single relative memory address associated with an address specified by the received command. The memory controller assembles a sub-request comprising a single contiguous instruction portion, which includes the single relative memory address and one or more instructions to perform the memory operation, and the respective data division, the respective data division following the single contiguous instruction portion, and transmits the sub-request to every memory portion of the number of memory portions of the individual memory device.

Locally generating and storing RAID stripe parity with single relative memory address for storing data segments and parity in multiple non-volatile memory portions

In the present disclosure, a persistent storage device includes both persistent storage, which includes a set of persistent storage blocks, and a storage controller. The persistent storage device stores and retrieves data in response to commands received from an external host device. The persistent storage device stores data, from a contiguous data block, to two or more sets of logical address blocks in persistent storage. The persistent storage device also retrieves data, corresponding to a contiguous data block, from two or more sets of logical address blocks in persistent. In both instances, the two or more sets of logical address blocks in persistent storage, in aggregate, are not contiguous.

Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device

A persistent storage device includes both persistent storage, which includes a set of persistent storage blocks, and NVRAM, and in particular a set of NVRAM blocks. The persistent storage device also typically includes a storage controller. The persistent storage device, in addition to responding to commands to write data directly to and to read data directly from persistent storage blocks is also configured to write data to specified NVRAM blocks (e.g., specified by a host NVRAM write command) and to transfer data from a specified NVRAM block to a specified persistent storage block. As a result, multiple writes to a particular persistent storage block can be replaced with multiple writes to an NVRAM block and a subsequent single write to the particular persistent storage block. This reduces the number of writes to persistent storage and also reduces the number of corresponding block erase operations.

Persistent storage device with NVRAM for staging writes

A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Flash storage controller execute loop

Mass storage controller volatile memory containing metadata related to flash memory storage

A single command initiates a first read operation and sequence of one or more additional read operations from the same portion of memory. The one or more additional read operations are terminable after the first read operation provides a first plurality of data values that is made available to a requesting device and/or module. In some implementations, the first plurality of data values includes hard information values. Subsequent pluralities of data values are generated from the same portion of memory until a terminating event occurs. In some implementations, until a terminating event occurs, a respective hybrid plurality of data values is generated by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values. Each hybrid plurality of data values is representative of a corresponding plurality of soft information values.

Performance optimization of data transfer for soft information generation

A storage controller has multiple processors, divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In some embodiments, the storage controller operates with a flash memory module, and includes a first processor group, a second processor group and a third processor group, each having one or more processors for handling a different stage of a pipelined execution of host storage commands. With respect to a first host command, a first processor of the first processor group, a first processor of the second processor group, and a first processor of the third processor group comprise a first pipeline, and with respect to a second host command, a second processor of the first processor group, a second processor of the second processor group, and a second processor of the third processor group comprise a second pipeline.

Multiprocessor storage controller

Growing community of inventors

Morgan Hill, CA, United States of America

Aaron Keith Olbrich