Intel Corporation

Aaron K Martin

Stephen R Mooney

Bryan K Casper

James E Jaussi

Matthew B Haycock

Joseph T Kennedy

Shekhar Yeshwant Borkar

James A McCall

Mamun Ur Rashid

Mozhgan Mansuri

Roger K Cheng

David J Comer

Christopher P Mozak

Joe Salmon

Taner Sumesaglam

Derek M Conrow

Ganesh Balamurugan

Rajendran Nair

William Dawson Kesling

Ravindran Mohanavelu

Alex Thomas

Hing Yan To

Frank Patrick O'Mahony

Navneet Dour

Ying Zhou

Ajay Balankutty

Hsien-Pao Yang

Hon-Mo Raymond Law

Krishnamurthy Venkataramana

Kuan Zhou

Sridhar Tirumalai

Quoc Nguyen

Mohammed G Mostofa

Suwei Chen

Hari Venkatramani

Pavan Kumar Kappagantula

Moonkyun Maeng

Kuljit Singh Bains

Siva G Narendra

Stefan Rusu

John B Halbert

Zuoguo Wu

Robert J Royer, Jr

David Zimmerman

Andrew W Martwick

Jun Shi

Ritesh B Trivedi

Tomer Levy

Dawson Kesling

Timothy M Wilson

Harishankar Sridharan

Amaresh Pangal

Todd A Hinck

Jonathan Nick Spitz

Hariprasath Venkatram

Michael Sandhinti

Hsiao-Ching Chuang

Hon Mo Law

Rajesh Inti

Tanay Karnick

Noam Lupovich

Alex P Thomas

In a memory subsystem, a memory controller can put its physical interface (PHY) into a low power state when an associated memory device is in self-refresh. Instead of powering on the interface and then triggering the memory device to exit self-refresh, or instead waiting for the physical interface to be powered up prior to waking the memory device from self-refresh, the memory controller can instruct the PHY to send a self-refresh exit command to the memory device and power up the physical interface in parallel with the memory device coming out of self-refresh. The memory controller can power down a high speed clock path of the PHY and use a slower clock path to send the self-refresh exit command before powering the high speed clock path back up.

Fast self-refresh exit power state

An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)

An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

Dual power I/O transmitter

An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.

Dynamic reconfigurable dual power I/O receiver

Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

Reconfigurable clocking architecture

Described is an apparatus which comprises: a first feedback loop to generate a control signal for regulating an output voltage provided to a load; and a second feedback loop, separate from the first feedback loop, to receive the control signal from the first feedback loop, the second feedback loop to regulate the output voltage provided to the load.

Mixed signal low dropout voltage regulator with low output impedance

Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations.

Converged adaptive compensation scheme

Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces

A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.

I/O driver transmit swing control

Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed.

Memory receiver circuit for use with memory of different characteristics

A method and apparatus for transceiver clock architecture with transmit PLL and receive slave delay lines. In one embodiment, the method includes the generation of a transmitter (Tx) clock signal by adjusting a control voltage of a voltage controlled oscillator to lock a phase and frequency of Tx clock signal to a reference clock signal. In one embodiment, a frequency of the Tx clock signal is a multiple of a frequency of the reference clock signal. In one embodiment, a slave delay line may be used, including a plurality of variable delay buffers that are configured according to the control voltage to generate a receiver (Rx) clock signal in response to a received clock signal that is synchronized with the reference clock signal. The Rx clock signal may be provided to data recovery logic to sample data. Other embodiments are described and claimed.

Transceiver clock architecture with transmit PLL and receive slave delay lines

An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

Low swing voltage mode driver

Described is an integrated circuit (IC) which comprises: an input-output (I/O) pad for coupling to a transmission line; a voltage mode driver coupled to the I/O pad, the voltage mode driver having a pull-up driver and a pull-down driver; and a current mode driver coupled to the I/O pad, the current mode driver operable to function in parallel to the voltage mode driver.

Transmitter with voltage and current mode drivers

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Hillsboro, OR, United States of America

Aaron K Martin