Alliance for Sustainable Energy, LLC

Wisconsin Alumni Research Foundation

Rochester Institute of Technology

Aaron Joseph Ptak

John David Simon

Kevin Louis Schulte

Andrew Gordon Norman

David Levi Young

Thomas Francis Kuech

William Edwin McMahon

Yong Lin

Kirstin Alberi

Brelon James May

Elisabeth Lynne Mcclure

Wondwosen Tilahun Metaferia

Disclosed herein are methods and devices that use a low-thermal conductivity inert gas to shield reactant gases and thus enabling a cold wall operation within a hot wall system.

Nitrogen-enabled high growth rates in hydride vapor phase epitaxy

The present disclosure relates to a method that includes depositing a first layer onto a substrate, depositing a second layer onto a surface of the first layer, and separating the substrate from the second layer, where the substrate includes a first III-V alloy, the second layer includes second III-V alloy, and the first layer includes a material that includes at least two of a Group 1A element, a Group 2A element, a Group 6A element, and/or a halogen.

Epitaxial alkali halide layers for III-V substrate recycling

The present disclosure relates to a method that includes contacting a surface of a first layer that includes a Group III element and a Group V element with a gas that includes HCl, where the first layer is positioned in thermal contact with a wafer positioned in a chamber of a reactor, and the contacting results in a roughening of the surface.

Light scattering structures for thin-film solar cells and methods of making the same

Presented herein are reactors for growing or depositing semiconductor films or devices. The reactors disclosed may be used for the production of III-V materials grown by hydride vapor phase epitaxy (HVPE).

Hydride enhanced growth rates in hydride vapor phase epitaxy

A reactor for growing or depositing semiconductor films or devices. The reactor may be designed for inline production of III-V materials grown by hydride vapor phase epitaxy (HVPE). The operating principles of the HVPE reactor can be used to provide a completely or partially inline reactor for many different materials. An exemplary design of the reactor is shown in the attached drawings. In some instances, all or many of the pieces of the reactor formed of quartz, such as welded quartz tubing, while other reactors are made from metal with appropriate corrosion resistant coatings such as quartz or other materials, e.g., corrosion resistant material, or stainless steel tubing or pipes may be used with a corrosion resistant material useful with HVPE-type reactants and gases. Using HVPE in the reactor allows use of lower-cost precursors at higher deposition rates such as in the range of 1 to 5 &#x3bc;m/minute.

High throughput semiconductor deposition system

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices. The low-defect density semiconductor materials produced using this method result in the enhanced performance of the semiconductor devices that incorporate the semiconductor materials.

Methods of producing free-standing semiconductors using sacrificial buffer layers and recyclable substrates

Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline InGaAlN alloy. The lattice parameter of the InGaAlN or other group III-nitride alloy may be related to the substrate lattice parameter by (a&#x2032;)=&#x221a;2(a) or (a&#x2032;)=(a)/&#x221a;2. The semiconductor alloy may be prepared to have a selected band gap.

Lattice matched crystalline substrates for cubic nitride semiconductor growth

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.

Lattice matched semiconductor growth on crystalline metallic substrates

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a&#x2032;) maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.

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Littleton, CO, United States of America

Aaron Joseph Ptak