Qualcomm Incorporated

National Semiconductor Corporation

Aaron Douglass Lamb

Christopher G Lott

Michael Goldfarb

Erich Plondke

Eric W Mahurin

Dexu Lin

Prajakt Kulkarni

David J Hoyle

Somdeb Majumdar

Ren Li

Rexford Alan Hill

Lawrence Jarrett Malone

Amin Ansari

Karamvir Chatha

Suren Mohan

Albert Danysh

Edward Liao

The present disclosure describes methods, computer-readable media, and apparatuses for operating neural networks. For example, a first apparatus may receive a set of sparse weight vectors. The first apparatus may compress the set of sparse weight vectors to produce a compressed set of sparse weight vectors. The first apparatus may operate a neural network based on the compressed set of sparse weight vectors. In another example, a second apparatus may receive a set of sparse weight vectors. The second apparatus may perform a sparse computation based on the set of sparse weight vectors, and the performance of the sparse computation may produce one or more partial sums. The second apparatus may operate a neural network based at least in part on the one or more partial sums.

Compression of sparse deep convolutional network weights

A method of exploiting activation sparsity in deep neural networks is described. The method includes retrieving an activation tensor and a weight tensor where the activation tensor is a sparse activation tensor. The method also includes generating a compressed activation tensor comprising non-zero activations of the activation tensor, where the compressed activation tensor has fewer columns than the activation tensor. The method further includes processing the compressed activation tensor and the weight tensor to generate an output tensor.

Exploiting activation sparsity in deep neural networks

A method of constraining data represented in a deep neural network is described. The method includes determining an initial shifting specified to convert a fixed-point input value to a floating-point output value. The method also includes determining an additional shifting specified to constrain a dynamic range during converting of the fixed-point input value to the floating-point output value. The method further includes performing both the initial shifting and the additional shifting together to form a dynamic, range constrained, normalized floating-point output value.

Constraining function approximation hardware integrated with fixed-point to floating-point conversion

Certain aspects of the present disclosure are directed to methods and apparatus for circular floating point addition. An example method generally includes obtaining a first floating point number represented by a first significand and a first exponent, obtaining a second floating point number represented by a second significand and second exponent, and adding the first floating point number and the second floating point number using a circular accumulator device.

Circular accumulator for floating point addition

Computing a non-linear function &#x192;(x) in hardware or embedded systems can be complex and resource intensive. In one or more aspects of the disclosure, a method, a computer-readable medium, and an apparatus are provided for computing a non-linear function &#x192;(x) accurately and efficiently in hardware using look-up tables (LUTs) and interpolation or extrapolation. The apparatus may be a processor. The processor computes a non-linear function &#x192;(x) for an input variable x, where &#x192;(x)=g(y(x),z(x)). The processor determines an integer n by determining a position of a most significant bit (MSB) of an input variable x. In addition, the processor determines a value for y(x) based on a first look-up table and the determined integer n. Also, the processor determines a value for z(x) based on n and the input variable x, and based on a second look-up table. Further, the processor computes &#x192;(x) based on the determined values for y(x) and z(x).

Approximation of non-linear functions in fixed point using look-up tables

Certain aspects of the present disclosure provide methods and apparatus for producing programmable probability distribution function of pseudo-random numbers that can be utilized for filtering (dropping and passing) neuron spikes. The present disclosure provides a simpler, smaller, and lower-power circuit than that typically used. It can be programmed to produce any of a variety of non-uniformly distributed sequences of numbers. These sequences can approximate true probabilistic distributions, but maintain sufficient pseudo-randomness to still be considered random in a probabilistic sense. This circuit can be an integral part of a filter block within an ASIC chip emulating an artificial nervous system.

Method and apparatus for producing programmable probability distribution function of pseudo-random numbers

An FSK receiver comprising: 1) demodulation circuitry for receiving an incoming FSK signal and generating a baseband signal comprising an amplitude modulated symbol stream, of Logic 0 symbols and Logic 1 symbols having a data rate, R; 2) auto-correlation circuitry for sampling the baseband signal S times during each symbol and generating an auto-correlation function comprising a sample stream of N-bit samples having a data rate, S&#xd7;R, and having positive-going peaks approximately coinciding with the center of the Logic 1 symbol in a 010 sequence in the baseband signal and negative-going peaks approximately coinciding with the center of the Logic 0 symbols in a 101 sequence in the baseband signal; and 3) decision circuitry for receiving the auto-correlation function and deciding a logic level of a first symbol as a function of: 1) a comparison of a signal level of a center sample of the first symbol and a mean signal level of the auto-correlation function and 2) a comparison of the signal level of the center sample of the first symbol and a signal level of a center sample of a second symbol preceding the first symbol.

Apparatus and method for FSK demodulation with integrated time and frequency tracking

A radio frequency (RF) transceiver having improved low power operating modes. The RF transceiver comprises: 1) a radio frequency (RF) modem section comprising: a) receive path circuitry for receiving and down-converting an incoming RF signal to thereby produce an incoming baseband signal; and b) transmit path circuitry for receiving and up-converting an outgoing baseband signal to thereby produce an outgoing RF signal; 2) a baseband section comprising baseband circuitry for receiving and processing the incoming baseband signal and for generating the outgoing baseband signal; and 3) a power-saving apparatus for determining that the baseband section is idle and, in response to the determination, reducing a power supply voltage providing power to the baseband section.

Apparatus and method for reducing power consumption in wireless RF systems

A signal detection circuit for receiving a digital baseband signal comprising an amplitude modulated symbol stream of Logic 0 symbols and Logic 1 symbols, each of the Logic 0 and Logic 1 symbols comprising S sequential samples, wherein the amplitude modulated symbol stream contains a preamble of N known symbols preceding a plurality of user data symbols. The signal detection circuit comprises: A) a signal mean determination circuit that receives G samples from the digital baseband signal and determines an amplitude mean value associated with the amplitude modulated symbol stream; and B) a correlation circuit that detects the preamble.

Apparatus and method for signal acquisition in a FSK demodulator with integrated time and frequency tracking

An FSK receiver comprising: 1) demodulation circuitry for receiving an incoming FSK signal and generating a baseband signal comprising an amplitude modulated symbol stream of Logic 0 symbols and Logic 1 symbols having a data rate, R; 2) auto-correlation circuitry for sampling the baseband signal S times during each symbol and generating an auto-correlation function comprising a sample stream of N-bit samples having a data rate, S&#xd7;R, and having positive-going peaks approximately coinciding with the center of the Logic 1 symbol in a 010 sequence in the baseband signal and negative-going peaks approximately coinciding with the center of the Logic 0 symbols in a 101 sequence in the baseband signal; and 3) decision circuitry for receiving the auto-correlation function and deciding a logic level of a first symbol as a function of: 1) a comparison of a signal level of a center sample of the first symbol and a mean signal level of the auto-correlation function and 2) a comparison of the signal level of the center sample of the first symbol and a signal level of a center sample of a second symbol preceding the first symbol.

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San Diego, CA, United States of America

Aaron Douglass Lamb