Everspin Technologies, Inc.

Green Mountain Semiconductor Inc.

Aaron D Willey

Jieming Qi

Wolfgang Hokenmaier

Ryan A Jurasek

Donald W Labrecque

Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.

Single-lock delay locked loop with cycle counter and method therefor

Single-lock delay locked loop with cycle counter and method therefore

An extremely dense, high speed, and low power content addressable DRAM is presented. To enable a parallel searching, a data word to be searched may be driven onto column select lines (CSLs) of a DRAM array. Although two or more primary sense amplifiers typically are not connected at the same time to the same local data line during operation of a DRAM, in various embodiments presented herein, some or all sense amplifiers in a DRAM can be activated simultaneously to enable maximum parallelism with local data line sharing being explicitly allowed. Using this architecture, a data word can be simultaneously searched in all banks and with multiple wordlines. Since no input/output transactions are required and no data needs to be driven from the bank during execution of a search, overall current, and thus power usage, can be reduced.

Content addressable dynamic random-access memory with parallel search functionality

Growing community of inventors

South Burlington, VT, United States of America

Aaron D Willey