Unisys Corporation

Aaron C Peterson

Larry L Byers

Eugene A Rodi

Clarence W DeKarske

Gerald J Maciona

Joseph G Kriscunas

Jeff A Engel

A system and method for increasing the throughput of a directory-based storage system is provided. The storage system includes a data storage system to store data signals, and a directory to store state information for the data signals. Requests issued to the storage system are grouped into sets. The requests within a same set are issued in succession to the data storage system to initiate read and/or write memory operations. At the same time, directory entries are read from the directory for each request in the set. Each directory entry is updated as it is retrieved to reflect the requested memory operation. After all directory entries are retrieved, the updated entries are stored back to the directory in succession so that the bi-directional interface to the directory undergoes only a single direction change during the processing of the set.

System and method for increasing bandwidth in a directory based high speed memory system

An apparatus for efficiently testing a plurality of memory devices at the board level. The logic for the present invention is minimal and can be placed on a controller chip within the board design. In addition, the interconnect lines between the controller chip and each of the plurality of memory devices can also be tested. Finally, the present invention requires minimal setup time and performs a functional test of the memories in a very short period of time.

Built-in-self-test scheme for testing multiple memory elements

A high-speed partitioned set associative cache memory is provided with a plurality of cache memory boards. Each of the boards is provided with a partial data array and a full tag array on each board. At least one memory address register is mounted on each of the boards with the partial data array and the full tag array for receiving a unique address from the central processing unit which enables the plurality of memory address registers to simultaneously access addresses in the partial data arrays on different boards and to also address tag addresses associated with the data addresses by sequencing controls mounted on a separate board with logic circuits which monitor output signals from the data arrays and the tag arrays. The output signals resulting from accessing memory locations in the cache memory are coupled to logic circuits for determining the type of error and the exact array where a single error has occurred.

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Saint Paul, MN, United States of America

Aaron C Peterson