Alliant Techsystems Inc.

Cubic Corporation

Aaron C Caba

Masud Beroz

Kenneth J Vanhille

Anatoliy Boryssenko

Steven Edward Huettner

Timothy Amis Smith

Jared Williams Jordan

Joseph O Bellotte

Thomas F Farabaugh

A microelectronic structure having CTE compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween.

CTE compensation for wafer-level and chip-scale packages and assemblies

In one example, a rocket nozzle assembly is disclosed that has stowed and deployed positions, and includes a casing including an outer wall and an inner surface, at least a portion of the inner surface defining a diverging region, wherein the casing defines a plurality of fin slots, and wherein each of the plurality of fin slots extend through the outer wall of the casing and the inner surface of the casing, and wherein the diverging region defines a bell-shaped contour. The assembly further includes a plurality of fins pivotally engaged to the casing, wherein in the stowed position, each of the plurality of fins extends into the diverging region through a respective one of the fin slots, and wherein in the deployed position, each of the plurality of fins extend outwardly from the casing.

Rocket nozzle assembly

Growing community of inventors

Blacksburg, VA, United States of America

Aaron C Caba