Cadence Design Systems, Inc.

Aaron Beverly

Luciano Lavagno

Eamonn O'Brien-Strain

Christopher Edward Hoover

Neeti Khullar Bhatnagar

Qizhang Chao

Massimiliano L Chiodo

Sherry Solden

Edwin A Harcourt

Prakash Parikh

Douglas D Dunlop

Poonam Agrawal

Soumya Desai

Shampa Gupta

William W La Rue, Jr

Hungming Chou

Michael D Sholes

Sanjay Chakravarty

Franco Carbognani

A method and system for evaluating performance level models of electronic systems having both hardware and software components is provided. The system and method allow for the simplified implementation and testing of several different architectural designs for compliance with the desired operational requirement of a designed electronic system.

Method and system for performance level modeling and simulation of electronic systems having both hardware and software elements

A method and mechanism for performing improved performance analysis upon transaction level models. A system block may be modeled using transaction model at different levels of abstraction. A testbench may be used to apply a set of stimuli to a transaction model (e.g. a TLM model) and a RTL equivalent model, and store the resulting timing information into a database. The timing information stored in the database may be used to validate the performance of the transaction models and system block. The testbench may analyze transaction models in the TLM domain and the RTL domain through the employment of TVM (transaction verification models) which are components that maps the transaction-level requests made by a test stimulus generator to a detailed signal-level protocol on the RTL design.

Method and mechanism for improved performance analysis in transaction level models

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Los Gatos, CA, United States of America

Aaron Beverly