Cadence Design Systems, Inc.

Other

Broadcom Corporation

Aamir A Farooqui

Vojin G Oklobdzija

Farzad Chehrazi

David Lawrence Heine

David K Chin

Wei-Jen Li

Andy W Yu

An approach is described for a method and apparatus for a low energy programmable vector processing unit for use in processing such as for example neural network backend processing. According to some embodiments, this approach provides a pooling/vector processing unit for performing backend processing that implements a single issue multiple data (SIMD) datapath that performs various backend processing functions using only a single instruction. For instance, the present approach provides an apparatus and method for execution of operations in parallel using a single issued instruction to a plurality of processing cells. In some embodiments, there are multiple groups of processing cells for performing different operations&#x2014;e.g. pooling, permute, sigmoid/tanh, and element wise operations. In some embodiments, the single instructions are provided by a programmable controller within the pooling/vector processing unit for issuing instructions which manages the retrieval and issuance of instructions within the pooling/vector processing unit.

Method and apparatus for a low energy programmable vector processing unit for neural networks backend processing

The present disclosure relates to a system and method for use in a digital signal processing environment. Embodiments may include a programmable processor configured to execute an instruction set that includes multiply instructions and/or multiply-accumulate instructions that generate a result in carry-save format or redundant binary format. The instruction set may be executed at a single instruction, multiple data (SIMD) level.

System and method for a low-power processing architecture

A single block shifter design performing arithmetic and logical shift operations on input operands of multiple types is disclosed. The shifter design may be configurable and automatically generated to support multiple partition types including at least one of 80-bit, 40-bit, and 20-bit partition type. The shifter may also be configured and automatically generated to perform rotate operations on input operands. The shifter may include two stages where the first stage includes multiple multiplexers performing shift or rotate operations by one or more shift or rotate amounts without saturation, and the second stage includes multiple multiplexers performing operations with saturation. The shifter includes an inversion block to process signed and unsigned input data. A method of automatically generating the shifter design with an electronic design tool is also disclosed.

Universal shifter and rotator and methods for implementing a universal shifter and rotator

A single-instruction multiple-data (SIMD) multiplier-accumulator apparatus and method. A multiplier block with two 16-bit by 32-bit multiplier circuits transform a selectable number of input multipliers and multiplicands into a selected number of products. Each multiplier circuit comprises an array of full adders that generates and sums partial products using carry-save addition. An accumulator block, with additional data width to help prevent overflow, adds the products to a selectable number of input addends and outputs a number of results. Embodiments perform one to four multiplications together, depending on the number of bits (eight, 16, 24, or 32) selected for the input operands. Embodiments output 20-bit, 40-bit, or 80-bit multiply-accumulate results at rates of at least 1.1 GHz. Embodiments support signed inputs, negated multiplication products, and Q-format data. A hybrid sign extension management approach improves performance for 80-bit outputs.

Universal single instruction multiple data multiplier and wide accumulator unit

Methods and apparatus for an encryption processor for performing accelerated computations to establish secure network sessions. The encryption processor includes an execution unit and a decode unit. The execution unit is configured to execute Montgomery operations and including at least one adder and at least two multipliers. The decode unit is configured to determine if a square operation or a product operation needs to be performed and to issue the appropriate instructions so that certain multiply and/or addition operations are performed in parallel in the execution unit while performing either the Montgomery square or Montgomery product operation.

Encryption processor for performing accelerated computations to establish secure network sessions connections

A partitioned multiplier circuit which is designed for high speed operations. The multiplier of the present invention can perform one 32&times;32 bit multiplication, two 16&times;16 bit multiplications (simultaneously) or four 8&times;8 bit multiplications (simultaneously) depending on input partitioning signals. The time required to perform either the 32&times;32 bit or the 16&times;16 bit or the 8&times;8 bit multiplications is constant. Therefore, multiplication results are available with a constant latency regardless of operand bit-size. In one embodiment, the latency is two clock cycles but the multiplier circuit has a throughput of one clock cycle due to pipelining. The input operands can be signed or unsigned. The hardware is partitioned without any significant increase in the delay or area and the multiplier can provide six different modes of operation. In one embodiment, Booth encoding is used for the generation of 17 partial products which are compressed using a compression tree into two 64-bit values. This is performed in the first pipeline stage to generate a sum and a carry vector. These values are then added, in the second pipestage, using a carry propagate adder circuit to provide a single 64-bit result. In the case of 16&times;16 bit multiplication, the 64-bit result contains two 32-bit results. In the case of 8&times;8 bit multiplication, the 64-bit result contains four 16-bit results. Due to its high operating speed, the multiplier circuit is advantageous for use in multi-media applications, such as audio/visual rendering and playback.

High performance universal multiplier circuit

An improved Booth encoder/selector circuit having an optimized critical path. The Booth encoder has a number of inverters coupled to several of the input multiplier bits. The inverted/non-inverted multiplier bits are then fed as inputs to NAND gates as well as a series of pass gates. The outputs of the pass gates are then fed as inputs to other NAND gates. The output from the NAND gates serve as control signals for controlling the Booth selector. The Booth selector is comprised of inverters and pass gates. Multiplicand bits are input to the pass gates. The control signals generated by the Booth encoder are selectively coupled to the inverters and pass gates such that they control which one of a plurality of multiplicand bits are selected for output. Basically, the Booth selector functions as a multiplexer whereby one of the following is output: the multiplicand bit is multiplied by zero, multiplied by one, multiplied by negative one, multiplied by two, or multiplied by negative two. The Booth encoder/selector is used in a multiplier circuit to minimize the number of partial products. An adder is then used to sum all of the partial products to arrive at the final answer. In the present invention, the critical path has been optimized such that the overall speed of the multiplier is greatly improved.

Multiplier circuit having an optimized booth encoder/selector

A partitioned shift right logic circuit that is programmable and contains rounding support. The circuit of the present invention accepts a 32-bit value and a shift amount and then performs a right shift operation on the 32-bits and automatically rounds the result(s). Signed or unsigned values can be accepted. The right shift circuit is partitioned so that the 32-bit value can represent: (1) a single 32-bit number; or (2) two 16-bit values. A 1 bit selection input indicates the particular partition format. In operation, if the input value is not negative, then one (&ldquo;1&rdquo;) is added at the guard bit position and a right shift with truncate is performed. If the input is negative and the guard bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is one, then one is added at the guard bit position and a right shift with truncate is performed. The shift circuitry used by the present invention is fully partitioned to accept word or half-word input and contains multiple cascaded multiplexer stages for performing partitioned right shifting and supports signed shifting. Each multiplexer stage can be programmed to perform a selected shift amount (including,shift). The right shift circuit of the present invention can be used in multi-media applications and can also be used for general purpose and VLIW (very long instruction word) processor without performance degradation.

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Mountain View, CA, United States of America

Aamir A Farooqui