Honeywell International Inc.

Aad Van Wensen

Joseph Pradeep Felix

Adrianus Cornelis Maria Hamers

Alan R Foose

Quang Nguyen

A method is provided that provides data analysis for sequence of events reporting in the operation of an industrial process. A digital filter and edge detector are provided that combines a method for excluding known invalid samples and a method for excluding samples taken while the input in the traveling range. The filtering method reduces the overhead on the CPU from managing the sequence of events machine and allows it to focus on performing safety functions.

Digital input edge detection with smart filtering algorithm

A safety instrumented system (SIS) includes safety controllers, and safety input/output (I/O) modules coupled to safety field devices that are coupled in parallel with a process control system's field devices to processing equipment which is configured and controlled to run a process. An I/O mesh network between the safety controllers and the safety I/O modules is configured for selecting any safety controller to become coupled to any safety I/O module to function as a pool of safety I/O modules so that any safety controller is configurable to receive sensor signals from and transmit control signals to any safety field device. The safety field devices are for monitoring process variable(s) for the process so that when one of the safety controllers recognizes a hazardous condition regarding the processing equipment, the SIS independently takes action to keep the processing equipment under control or bring it to a safe state.

I/O mesh architecture for a safety instrumented system

A fault-tolerant process control system includes a first and second master process controller, each including a first and second serial communication engine. A first bus switch couples the first serial communication engine to a shared SPI bus and a second bus switch couples the second communication engine to shared SPI bus. The shared SPI bus transmits SPI signals received from the first serial communication engine when the first bus switch is enabled to a first target device, and transmits SPI signals received from the second serial communication engine when the second bus switch is enabled to a second target device. An arbiter block receives a select control signal from the master process controllers and is coupled to both the first and second bus switch for single bus switch selection so that only one master process controller is granted access to the shared SPI bus.

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Tilburg, Netherlands

Aad Van Wensen