Intel Corporation

A Leonard Brown

Vivek Garg

Asit K Mallick

Ian M Steiner

Adriaan Van De Ven

Malini Krishnan Bhandaru

Scott P Bobholz

Matthew M Bace

Eric Dehaemer

Methods and apparatus for using per task time slice information to improve dynamic performance state selection are described. In one embodiment, a new performance state is selected for a process based on one or more previous execution time slice values of the process. Other embodiments are also described.

Using per task time slice information to improve dynamic performance state selection

A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

Processor having per core and package level P0 determination functionality

Growing community of inventors

Weston, MA, United States of America

A Leonard Brown