Qualcomm Incorporated

A Chris Irvine

Jeffrey Alexander Levin

Judith LaRocca

Senthil Kumar Govindaswamy

Jeff A Levin

An apparatus to determine the inverse transform of a block of encoded data the block of encoded data comprising a plurality of compressed frequency domain data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

Apparatus and method for decoding and computing a discrete cosine transform using a butterfly processor

An apparatus and method for minimizing the code length of an input address for at least one for variable length encoded data is claimed. A block of variable length encoded data is read. The block of variable length encoded data is then converted into sub-optimall encoded data. The variable length encoded data is defined in having a prefix portion and a suffix portion. The prefix portion of the variable length encoded data is used to signify the look-up table. The suffix portion of the variable length encoded data is used as an input address for the look-up table.

Sub-optimal variable length coding

An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

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Bonsall, CA, United States of America

A Chris Irvine