Inventor Recognitions with Centurion Plus Utility Patents as of May 9, 2023

Guodong Zhang is Sr. Principal Engineer at InterDigital Inc.

He received MS and Ph.D. in Electrical Engineering from Stony Brook University.

Patent №: 11647438 (May 9, 2023) –  Method and apparatus for monitoring downlink channels of a plurality of cells and receiving data over a downlink channel 

Patent №: 11647439 (May 9, 2023) – Method and apparatus for transmitting data over a downlink channel of at least one of a plurality of cells

Rui Xu

Beijing BOE technology development | BOE · Advanced Research Institute of Multidisciplinary Science

Doctor of Engineering.

Patent №: 11646323 (May 9, 2023) – Array substrate, display panel and display device

The present disclosure provides an array substrate for a display device with pixel structures arranged in rows and columns. It includes first driving signal wires and leads, including first-type leads and at least one second-type lead.

Thomas Vogelsang

Member of Rambus Labs in Sunnyvale, CA. He is working on cryogenic computing since 2018. After working on memory architectures for machine learning, his current focus is now on future DRAM devices and system architecture.

Mr.Vogelsang received the Infineon Innovations Award in 2001 for the design of the first 256 M DDR DRAM. His research interests are the design of low-power and high-speed DRAMs and the impact of technology development on circuit design.

He received the Dipl. univ. and Dr.rer.nat. degrees in physics from the Technical University of Munich in 1989 and 1993, respectively.

Douglas B. Gundel

He is Division Scientist at 3M.

Douglas received a BS degree in Chemistry from Millersville University of Pennsylvania in 1987; an M.S. and Ph.D. in Materials Science and Engineering from the University of Virginia, in 1991 and 1994.

Patent №: 11646131 (May 9, 2023) – Electrical cable with structured dielectric. The cable has parallel conductors lying in a plane and a dielectric film folded along a longitudinal line with pairs of structures, each pair facing and aligning with a conductor.

Marc A. Bergendahl

He is Process and Integration Engineer at IBM. Process and Equipment Support for Reactive Ion Etch tools. Integration support for N-1 node Health of line process flow.

Marc received a Master’s degree from Rensselaer Polytechnic Institute in 2001

Patent №: 11646235 (May 9, 2023) –  Vertical tunneling field effect transistor with dual liner bottom spacer. This is a method for fabricating vertical tunnelling field effect transistors (VFETs) with a dual-liner bottom spacer. The method involves forming a first liner on the top surface of a source or drain region and semiconductor fin sidewalls. A second liner is then formed on the first liner to collectively define the dual liner bottom spacer.