Centurion Patentors as of October 22, 2024

Michael Boers

Michael Boers received a B.E. degree in electrical engineering from the University of Sydney, Sydney, NSW, Australia, in 2005, and a Ph.D. degree from Macquarie University, Sydney, in 2014.

He was with Broadcom from 2009 to 2016, focusing on the development of transceivers.

Patent №: 12126073 (October 22, 2024) – Phased array antenna panel having reduced passive loss of received signals.

This describes a phased array antenna panel with two sets of antennas, two RF front-end chips, and a combiner RF chip. Each RF front-end chip processes input signals from its respective antenna set, generating output signals. The combiner RF chip then combines these output signals into one power-combined signal, either directly or via a power combiner.

Pascal Fornara

Memory Technology Program Manager at ST Microelectronics.

Patent №: 12125808 (October 22, 2024) – Method for protecting data stored in a memory, and corresponding integrated circuit.

A protection device includes a capacitive structure with a first conducting body connected to the floating gate, a dielectric body, and a second conducting body connected to ground. If an aqueous solution contacts the dielectric, it electrically couples the floating gate to ground, altering its charge and erasing the data.

Francesco La Rosa

Quality and Reliability Failure Analysis Senior Engineer presso Micron Technology.

Patent №: 12125533 (October 22, 2024) – Non-volatile memory device readable only a predetermined number of times.

This describes a non-volatile memory device with memory cells in two rows and N columns. Each cell has a state transistor selectable via a buried vertical selection transistor. Twin memory cells in each column share a selection gate. Bits are stored across adjacent memory cells, with successive bits stored in twin cells.

Karthik Vaidyanathan

Principal Engineer at Intel.

Patent №: 12125133 (October 22, 2024) – Speculative execution of hit and intersection shaders on programmable ray tracing architectures.

This disclosure describes a method for executing hit and intersection shaders in ray tracing. It uses SIMD or SIMT units for shaders and ray tracing circuitry to traverse rays through a hierarchical structure. Shader invocations are deferred and grouped until a trigger event, after which they are executed in a single batch.