Inventor Recognitions with Centurion Plus Utility Patents as of May 9, 2023
Welcome to the 9th of May 2023: Our goal is to celebrate the pioneering inventor recognitions who have reached noteworthy milestones in their fields this week.
Guodong Zhang is Sr. Principal Engineer at InterDigital Inc.
He received MS and Ph.D. in Electrical Engineering from Stony Brook University.
Patent №: 11647438 (May 9, 2023) – Method and apparatus for monitoring downlink channels of a plurality of cells and receiving data over a downlink channel
Patent №: 11647439 (May 9, 2023) – Method and apparatus for transmitting data over a downlink channel of at least one of a plurality of cells
Beijing BOE technology development | BOE · Advanced Research Institute of Multidisciplinary Science
Doctor of Engineering.
Patent №: 11646323 (May 9, 2023) – Array substrate, display panel and display device
The present disclosure provides an array substrate for a display device with pixel structures arranged in rows and columns. It includes first driving signal wires and leads, including first-type leads and at least one second-type lead.
Member of Rambus Labs in Sunnyvale, CA. He is working on cryogenic computing since 2018. After working on memory architectures for machine learning, his current focus is now on future DRAM devices and system architecture.
Mr.Vogelsang received the Infineon Innovations Award in 2001 for the design of the first 256 M DDR DRAM. His research interests are the design of low-power and high-speed DRAMs and the impact of technology development on circuit design.
He received the Dipl. univ. and Dr.rer.nat. degrees in physics from the Technical University of Munich in 1989 and 1993, respectively.
Patent №: 11646090 (May 9, 2023) – DRAM retention test method for dynamic error correction. This is a method for refreshing and testing the retention time of storage rows in an IC memory device, which includes interrupting the testing process if data access is requested for a given row under test.
Patent №: 11645212 (May 9, 2023) – Dynamic processing speed. The processing elements have direct access to memory banks on DRAMs in an integrated circuit stack. Rate calculation circuitry on the processor die determines the operating speed of processing elements and nodes based on operand size/type and memory bandwidth.
He is Division Scientist at 3M.
Douglas received a BS degree in Chemistry from Millersville University of Pennsylvania in 1987; an M.S. and Ph.D. in Materials Science and Engineering from the University of Virginia, in 1991 and 1994.
Patent №: 11646131 (May 9, 2023) – Electrical cable with structured dielectric. The cable has parallel conductors lying in a plane and a dielectric film folded along a longitudinal line with pairs of structures, each pair facing and aligning with a conductor.
He is Process and Integration Engineer at IBM. Process and Equipment Support for Reactive Ion Etch tools. Integration support for N-1 node Health of line process flow.
Marc received a Master’s degree from Rensselaer Polytechnic Institute in 2001
Patent №: 11646235 (May 9, 2023) – Vertical tunneling field effect transistor with dual liner bottom spacer. This is a method for fabricating vertical tunnelling field effect transistors (VFETs) with a dual-liner bottom spacer. The method involves forming a first liner on the top surface of a source or drain region and semiconductor fin sidewalls. A second liner is then formed on the first liner to collectively define the dual liner bottom spacer.
Inventors Recognitions with Centurion Plus Utility Patents as of May 23, 2023
October 10, 2023, Weekly Utility Patent Insights.
August 15, 2023, Weekly Utility Patent Insights
About The Author
Angelina Kushnarova
Angelina Kushnarova (Sverediuk) was born in Ukraine. She graduated from Ternopil Medical University with a specialization in Medicine and completed an internship in Radiology at Lviv University. She worked as a Radiologist, while also working as a web developer.